The present invention relates to circuits for receiving digital data arriving in series, and more specifically to the reception of digital data arriving with a variable frequency.
FIG. 1 is a diagram of a known receive circuit that comprises a “tracking” phase-locked loop circuit 1 providing a clock CLK activating a circuit (SAMPLER) 2 for sampling received data dr. Conventionally, circuit 1 comprises three elements connected in a loop: a phase detector 3, a filter circuit 4, and a voltage-controlled oscillator (VCO) 5. Phase detector 3 detects the phase shifts between rising edges of clock CLK and the transitions of the received data. Filter circuit 4 is a low-pass filter enabling filtering too fast phase variations that correspond to the input data jitter. As for voltage-controlled oscillator 5, it varies, after a given delay, the frequency of clock CLK under control of phase detector 3.
Sampler 2 provides as output data dS the samples of the received data dr sampled on each falling edge of clock CLK. The frequency of clock CLK being controlled by the frequency of the received data, the sequence of output data dS is thus normally identical to the sequence of received data dr.
When the frequency of the received data is stable, such a receive circuit operates very well once the edges of clock CLK of the tracking phase-locked loop circuit are in phase with the transitions of the received data. However, the use of such a receive circuit is much less reliable when the frequency of the received data varies. Indeed, for oscillator 5 to be able to vary the frequency of clock CLK sufficiently fast for its edges to be in phase with the transitions of the received data, filter circuit 4 must have a cut-off frequency much greater than that used in the case where the frequency is stable. The input noise is thus less filtered. The security margin is thus very reduced, or even non-existent, which may result in reception errors.
Further, the receive circuit often comprises analog circuits very sensitive to variations, especially of temperature and voltage, which results in generating noise on dock CLK and thus further decreasing the circuit reliability.